1. Field of the Invention
The present invention relates to a phase locked loop circuit. Particularly, the present invention relates to a phase locked loop circuit which is preferably used for a frequency synthesizer in a communication device.
2. Description of the Related Art
Conventionally, a phase locked loop(PLL) circuit is known as a circuit for synchronizing two clock signals.
Reference 1 describes that a typical phase locked loop circuit is preferably used for a communication device.
Reference 2 describes a phase locked loop circuit which implements a non-linear Io−Δφ characteristic.
Reference 3 describes a phase locked loop circuit which implements a linear Io−Δφ characteristic.
Reference 4 describes a phase locked loop circuit operable to control the pulse width of the UP signal and the pulse width of the DN signal.
Reference 1: S. Lo et al.,“A 1.8V/3.5 mA 1.1 GHz/300 MHz CMOS Dual PLL Frequency Synthesizer IC for RF Communications”, Proc. IEEE 1998 Custom Integrated Circuits Conference
Reference 2: Japanese laid-open patent publication No. 8-307258
Reference 3: Japanese laid-open patent publication No. 6-85664
Reference 4: Japanese laid-open patent publication No. 2000-349626
However, in any of the references mentioned above, reducing a phase noise in a locked state is not considered.
One of the purposes of the present invention is to provide a phase locked loop circuit which is capable of reducing a phase noise in a locked state.